AIT Community / Faculty / Research Scientists / Christoforos Kachris

CONTACT INFORMATION Christoforos Kachris, Ph.D. Researcher Athens Information Technology P.O. Box 68, 19.5 Km Markopoulo Avenue 19002 Peania, Attiki, Greece Phone: (+) 30-210-668-2792 e-mail: kachris [ a t ] ait . edu . gr Linkedin: http://www.linkedin.com/in/kachris

SUMMARY

Christoforos Kachris is a senior researcher at Athens Information Technology (AIT), Greece. He obtained his Ph.D. in Computer Engineering from Delft University of Technology, The Netherlands in 2007, and the diploma and the M.Sc. in Electronic and Computer Engineering from the Technical University of Crete, Greece in 2001 and 2003 respectively. From February 2009 till August 2010 he was a visiting assistant professor at the University of Crete, Greece and associate researcher at the Institute of Computer Science in the Foundation for Research and Technology (FORTH) working on the HiPEAC NoE and the SARC IP European research projects. In 2006 he was a research intern at Xilinx Research Labs, San Jose, CA, working at the Networks Group. From 2002 till 2003 he was working as an FPGA engineer in Ellemedia Technologies working on the European research project NPMADE (a multi-protocol residential gateway in FPGA). His research interests include:

• reconfigurable computing (FPGAs)  
• multi-processor SoC (MPSoC)  
• network processing  
• embedded systems  
• NoC interconnects  
• data center interconnects  
• computer architecture

Teaching:
Microprocessors and Embedded Systems (AIT36C), MSITT

RESEARCH/PROFESSIONAL EXPERIENCE

 EDUCATION 

PUBLICATIONS

Patents

1. Configurable Transactional Memory for Synchronizing Transactions, C. Kulkarni, C. Kachris, USA Patent number 12/114,567, Pub. Date Nov. 5, 2009

  Journals

1. C. Kachris, I. Tomkos, A Survey on Optical Interconnects for Data Centers, IEEE Communications Surveys and Tutorials, doi:10.1109/SURV.2011.122111.00069 [bibtex]

2. C. Kachris, C. Kulkarni, Transactional Memories for Multi-Processor FPGA Platforms, Journal of Systems Architecture, 2011, 57 (1), pp.160-168, doi:10.1016/j.sysarc.2010.10.005 [bibtex]

3. C. Kachris, S. Wong, S. Vassiliadis, Design and Performance Evaluation of an Adaptive FPGA for network applications, Microelectronics Journal, 2008, 40 (7), pp.1103-1110, doi:10.1016/j.mejo.2008.05.011 [bibtex]

4. L. Mhamdi, M. Hamdi, C. Kachris, S. Wong, S. Vassiliadis, High-Performance Switching Based on Buffered Crossbar Fabrics, Computer Networks Journal, 2006, 50 (13), pp. 2271-2285 [bibtex]

5. P.D. Dimitropoulos, C. Kachris, D.P. Karampatzakis, G.I. Stamoulis, A new SOI monolithic capacitive sensor for absolute and differential pressure measurements, Sensors and Actuators A: Physical, vol. 123-124, 2005, pp. 36-43 [bibtex]

6. A. Nikologiannis, I. Papaefstathiou, G.Kornaros, C. Kachris, An FPGA-based Queue Management System for High Speed Networking Devices, Elsevier Journal on Microprocessors and Microsystems, special issue on FPGAs, 2004, 28(5-6), pp. 223-236 [bibtex]

7. C. Kachris, N. G. Bourbakis, A. Dollas, A Reconfigurable Logic-Based Processor for the SCAN Image and Video Encryption Algorithm, International Journal of Parallel Programming, 2003, 31 (6), pp. 489-506 [bibtex]
    

 Conferences

1. G. Dimitrakopoulos. C. Kachris, E. Kalligeros, Scalable arbiters and multiplexers for on-FGPA interconnection networks, IEEE International Conference on Field Programmable Logic and Applications (FPL 2011), Chania, Greece, Sep 2011[bibtex]

2. C. Kachris, I. Tomkos, Power Consumption Evaluation of Hybrid WDM PON Networks for Data Centers, IEEE European Conference on Networks and Optical Communication (NOC 2011), Newcastle, UK, July 2011

3. Y. Gao, C. Kachris, M. Katevenis, An Efficient Sequential Iterative Matching Algorithm for CIOQ Switches, IEEE Symposium on Computers and Communications (ISCC 2011), Kerkyra (Corfu), Greece, June 2011[bibtex]

4. C. Kachris, G. Nikiforos, S. Kavadias, V. Papaefstathiou, M. Katevenis, Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface, IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig 2010), Cancun, Mexico, December 2010 [bibtex]

5. X. Yang, C. Kachris, M. Katevenis, Efficient Implementation for CIOQ Switches with Sequential Iterative Matching Algorithms, IEEE International Conference on Field-Programmable Technology (FPT 2010), Beijing, China, December 2010 [bibtex]

6. N. Chrysos, Lydia Y. Chen, C. Minkenberg, C. Kachris, M. Katevenis, End-to-end Congestion Management for Non-Blocking, Multi-stage Switching Fabrics using Commodity Switches, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2010), La Jolla, CA, October 2010 [bibtex]

7. C. Kachris, G. Nikiforos, V. Papefstathiou, S. Kavvadias, M. Katevenis, Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters, IEEE International Conference on Cluster Computing (Cluster 2010), Heraklion, Greece, September 2010 [bibtex]

8. C. Strydis, C. Kachris, G.N. Gaydadjief, ImpBench: A novel Benchmark Suite for biomedical, microelectronic implants, IEEE International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS'08), Samos, Greece, July 2008 [bibtex]
   Download ImpBench

9. C. Kachris, S. Vassiliadis, A Reconfigurable Platform for Multi-Service Edge Routers, ACM Symposium on Integrated Circuits and Systems Design, Rio de Janeiro, Brazil, September 2007 [bibtex]

10. C. Kachris, S. Vassiliadis, Design Space Exploration of Configuration Manager for Network Processing Applications, IEEE International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS'07), Samos, Greece, July 2007 [bibtex]

11. C. Kachris, C. Kulkarni, Configurable Transactional Memories, IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'07), Napa Valley, CA, April 2007 [bibtex]

12. C. Kachris, S. Vassiliadis, Design of a Web Switch in a Reconfigurable Platform, ACM/IEEE Symposium on Architectures for Network and Communication Systems (ANCS'06), San Jose, December 2006 [bibtex] 

13. C. Kachris, S. Vassiliadis, A Dynamically Reconfigurable Queue Scheduler, IEEE International Conference on Field Programmable Logic and Applications (FPL'06), Madrid, Spain, August 2006 [bibtex]

14. C. Kachris, S. Vassiliadis , Performance Evaluation of an Adaptive FPGA for Network Processing, IEEE Rapid Systems Prototyping (RSP'06), Chania, Greece, June 2006 [bibtex]

15. C. Kachris, S. Vassiliadis, Analysis of a Reconfigurable Network Processor, Reconfigurable Architectures Workshop (RAW'06)
    IEEE International Symposium on Distributed and Parallel Systems (IPDPS), Rhodos, Greece, April 2006 [bibtex]

16. L. Mhamdi, C. Kachris, S. Vassiliadis, A Reconfigurable Hardware Based Embedded Scheduler for Buffered Crossbar Switches, IEEE Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2006 [bibtex] 

17. A. Dollas, I. Ermis, I. Koidis, I. Zisis, C. Kachris, An Open TCP/IP Core for Reconfigurable Logic, IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'05), Napa Valley, CA, April 2005 [bibtex]

18. I. Papaefstathiou, G. Kornaros, T. Orphanoudakis, C. Kachris, Queue management in Network Processors, Design Automation and Test in Europe (DATE'05), Munich, Germany, March 2005 [bibtex]

19. C. Kachris, A. Dollas, N. Bourbakis, Performance Analysis of Fixed, and Custom Architectures for the SCAN Image and Video Encryption Algorithm, IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'03), Napa Valley, CA, April 2003 [bibtex]

20. C. Kachris, A. Dollas, N. Bourbakis, S. Maniccam, A Reconfigurable Logic-based Processor for the SCAN Image and Video Encryption Algorithm, Workshop on Application Specific Processors (WASP 2002), Istanbul, Turkey, November 2002

 Posters: 

1. C. Kachris, I. Tomkos, Energy-efficient Bandwidth Allocation in Optical OFDM-based Data Center Networks, OFC 2012, JTh2A.34

2. C. Kachris, E. Giacoumidis, I. Tomkos, Energy-efficient Study of Optical OFDM in Data Centers, OFC 2011, JWA087

 Scopus Citations

Thesis Supervised:

• XML processing in hardware for Reconfigurable Optical Networks, Nikolaos Gavalas, AIT-MSITT, 2011
• Architectures and Scheduling Mechanisms for Optical Interconnects, Pylarinos Miroslav, AIT-MSITT, 2011
• Network Traffic Measurment using the NetFPGA platfrom, Vasilis Koutsoubos, University of Crete, 2010
• Design of a cookie-based WebSwitch on the NetFPGA Platfrom, Salvator Galea, University of Crete, 2010

Professional Membership

• IEEE
• ACM
• HiPEAC NoE
• GreenTouch
• Member of Technical Chamber of Greece

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